1. Field of the Invention
The present invention relates generally to methods for manufacturing semiconductor packages. More particularly, the present invention relates to methods for manufacturing lead-on-chip (LOC) semiconductor packages in which leads of a lead frame are attached to a chip by an adhesive layer which is formed from a liquid adhesive applied to a bottom surface of the leads.
2. Description of the Related Art
As the integration density of a semiconductor integrated circuit (IC) device increases, so does the size of the semiconductor chip. However, to meet a demand for smaller and smaller devices, there are continuing efforts to reduce the size of the semiconductor chip packages. Various packaging technologies have been developed to meet this need for package miniaturization. One of them is the lead-on-chip (LOC) package technology in which a plurality of leads are disposed on and attached to the active surface of a semiconductor chip.
A lead frame of a typical semiconductor chip package includes a chip pad or a die pad on which the chip is mounted, and a plurality of leads which extend from the chip pad. On the other hand, the LOC package does not require a chip pad since the chip is directly attached to the leads. Accordingly, the ratio of the size of the chip to the size of the package is quite high. Other advantages of the LOC package are lead frame design flexibility and enhanced electrical performance.
A conventional LOC semiconductor package 100 is depicted in FIG. 1A in cross section showing a semiconductor chip 10, a lead frame 20, and an adhesive tape 30. FIG. 2A shows the spatial distribution of the lead frame 20, the chip 10, and the adhesive tape 30 in exploded perspective. FIG. 1B and FIG. 2B show enlarged views of portion `C` in FIG. 1A and `D` in FIG. 2A, respectively. As shown, a plurality of inner leads 22 of the lead frame 20 are attached to an active surface 12 of the chip 10. Physical adhesion between the lead frame 20 and the chip 10 is accomplished by adhesive tapes 30, while electrical interconnection between both is accomplished by bonding wires 40 connecting inner leads 22 to electrode pads 14.
A plurality of electrode pads 14 are formed along the center of the active surface 12 of the chip 10. The inner leads 22 are spaced apart so that the central electrode pads 14 are exposed between the opposing rows of the inner leads 22 on each side of the lead frame 20. Each inner lead 22 is electrically connected to a corresponding electrode pad 14. Each of the inner leads 22 is brought in close proximity to the respective corresponding electrode pad 14, and thus the lead frame 20 can be connected electrically to the chip 10 by means of short bonding wires 40.
Outer leads 24 extend outwardly from a package body 50, and are mounted to an exterior circuit board (not shown) after completing the entire packaging process. The package body 50 is formed from an encapsulant such as epoxy molding compound (EMC) in order to protect the chip 10, the inner leads 22, and the bonding wires 40 from hostile external environments. Dam bars 26, which are located across the inner leads 22 and the outer leads 24, not only impart some rigidity to the lead frame 20, but also prevent overflow of encapsulant during the encapsulation process. Therefore, the dam bars 26 fix the boundaries of the area where the package body 50 is formed. The dam bars 26 are removed after the encapsulation process, and so do not exist in the package 100 shown in FIG. 1. Tie bars 28 inside the package body 50 support the package 100 after the encapsulation process is completed.
The adhesive tape 30 typically comprises three layers. There is an adhesive layer 34, such as thermoplastic epoxy, on both sides of a center layer formed of a polyimide base film 32.
The assembly process of the conventional LOC package 100 is described next. First, solid adhesive tape 30 is applied to the bottom of a lead frame. Then, a chip 10 is positioned under the lead frame 20. The lead frame 20 with adhesive tape 30 may be baked so as to eliminate moisture from interfaces between the lead frame 20 and the adhesive tape 30, or between the layers 32, 34 in the adhesive tape 30. Then, the adhesive tape 30 on the frame is brought into contact with the active surface 12 of the chip 10 under high temperature to attach the lead frame 20 to the chip 10. After this, various conventional steps are conducted in succession to complete the packaging process. The steps may include electrical interconnection using the bonding wires 40, encapsulation for forming the package body 50, removal of the dam bars 26, and reshaping of the outer leads 24.
Though an advancement over other packages types in many respects, the conventional LOC packages employing the solid adhesive tape have some disadvantages. One problem is the structure of the adhesive tape itself. Since the adhesive tape consists of three layers, four interfaces exist between the chip and the lead frame. The interfaces between these two heterogeneous materials can produce thermal and mechanical stresses that can result in delaminations (i.e., separations at the interfaces), and in accompanying cracks of the package body. Furthermore, such package cracking may be accelerated by moisture absorption at the interfaces of the adhesive tape.
Another problem is associated with the production process for the adhesive tape itself. The solid three-layer adhesive tape is made by a several step process. The adhesive materials must be coated on one side of the base film and cured, and then also coated on the other side of the base film and cured again. Accordingly, the tape production process is complicated. In addition, the finished adhesive tape is difficult to handle since it has adhesive layers on both sides. Furthermore, the adhesive tape contains an expensive polyimide base film, which consequently results in a high production cost for the tape.